1. Technical Field
This disclosure relates to stack capacitors for semiconductor devices and more particularly, to an improved method and apparatus for capacitor electrodes suitable for use with feature sizes of .15 microns and beyond.
2. Description of the Related Art
Semiconductor memory cells include capacitors accessed by transistors to store data. Data is stored by as a high or low bit depending on the state of the capacitor. The capacitor's charge or lack of charge indicates a high or low when accessed to read data, and the capacitor is charged or discharged to write data thereto.
Stacked capacitors are among the types of capacitors used in semiconductor memories. Stacked capacitors are typically located on top of the transistor used to access a storage node of the capacitor as opposed to trench capacitors which are buried in the substrate of the device. As with many electrical devices, high conductivity is beneficial for performance characteristics of stacked capacitors.
In semiconductor memories, such as dynamic random access memories (DRAM), high dielectric constant capacitor formation processes include deposition of highly dielectric materials. In one type of high dielectric constant capacitors, a layer of high dielectric constant materials, such as barium strontium titanium oxide (BSTO), is deposited in an oxidized atmosphere.
Referring to FIG. 1, a structure 2 with stacked capacitors is shown. Stacked capacitors 3 include two electrodes, a top electrode or storage node 4, (usually platinum) and a bottom electrode 12 separated by a dielectric layer 18. An access transistor 5 includes a gate 6 which when activated electrically couples a bitline 7 through a bitline contact 8 to a plug 14. Plug 14 connects to electrode 12 through a diffusion barrier 16 and charge is stored on electrode 12.
During fabrication of a conventional stacked capacitor 10 as shown in FIG. 2, a bottom electrode 12 is deposited and patterned on a dielectric layer 20. Prior to the formation of bottom electrodes 12 a plug 14 and a diffusion barrier 16 are formed in dielectric layer 20. Plug 14 is preferably polycrystalline silicon (polysilicon or poly). Electrode 12 is preferably formed of platinum (Pt) and is relatively thick. To form individual bottom electrodes, a reactive ion etch (RIE) process is preferably employed. This process has been known to be very difficult to perform on thick films. More difficulty is experienced when fabricating bottom electrodes 12 due to the tendency of the etched surface to taper.
Typically the etched surfaces taper at an angle of about 65.degree. or less as shown in FIG. 3. FIG. 3 indicates a maximum achievable height based on the best taper angle (65.degree.) condition. It is apparent that the maximum height of electrode 12 is limited due to the tapering. This limitation also limits a surface area of electrode 12 making it particularly difficult to implement for smaller feature sizes, such as for features sizes of about 0.15 microns.
Referring to FIG. 4, a noble metal sidewall compound stack design is shown. A dielectric layer 22 having a plug 24 formed therein has a barrier layer 26 formed on top of dielectric layer 22. Sidewalls 28 are formed from a noble metal such as Pt or Pt/Ir (iridium). Sidewalls 28 become the bottom electrode for the stacked capacitor. Also, a dielectric layer 30, such as an oxide, is applied as shown. This design does not suffer from the tapering as described above, however the formation of the metal sidewall requires good conformality which is difficult to achieve for sputtered metal on a vertical surface. Further, the electrode height is limited due to conformality problems of both the sidewall metal films and the high dielectric constant material (i.e. BSTO) which is deposited thereon in later steps.
Therefore, a need exists for a method and apparatus for improving the surface area of bottom electrode for stacked capacitors while maintaining an appropriate height of the bottom electrode. A further need exists for a bottom electrode suitable for use with a feature size of .15 microns or less.